1. Technical Field
The present invention relates to system debugging in general, and, in particular, to a method and apparatus for performing interconnect tracing. Still more particularly, the present disclosure relates to a method and apparatus for performing bus tracing in a data processing system having a distributed memory.
2. Description of the Related Art
As technology progresses, the amount of circuitry that needs to be integrated onto a single chip is ever increasing. Also, state of the art technologies now routinely allow for the packaging of multiple chips on a single module substrate. In addition, higher operating clock frequencies are utilized both inside chips and on interconnects between chips. While all of the above-mentioned advancements lead to systems with higher performance, they also present some very difficult problems during system development.
Typically, before a new system can be brought to market, the system must be tested in a laboratory environment in order find any logical and/or electrical defects that may exist in the hardware design of the system. The capturing of lengthy traces of interconnect (or bus) transactions is routinely required to isolate some of the defects. Also, extensive performance modeling and analysis are required during system development to fine tune design points such that the maximum possible performance can be achieved. The capturing of traces that represent typical instruction sequences used by many common applications, such as commercial database applications, is required as part of the performance modeling and analysis. Sometimes, those traces have to be very lengthy in order to adequately represent the target commercial applications.
Traditionally, the collection of traces has been performed by attaching several logic analyzers external to interconnects. The logic analyzers must be capable of sampling data at the same speed as the interconnects to which they are connected and must have very large memories to store lengthy traces. With the technological advances described above, the traditional method of collecting traces has become unworkable for several reasons. First, the speed of interconnects have increased to the point that most off-the-shelf logic analyzers are not fast enough for sampling data reliably, and those that can are prohibitively expensive. Second, even with logic analyzers that can perform at high speed, the increased loading on interconnects caused by the attached logic analyzers can degrade the integrity of the interconnects to a point that the interconnects cease to function at the desired frequency. Third, with the modern packaging technology, interconnects tend to be imbedded within a single chip and/or within a multichip module. Thus, even if the above-mentioned two problems can be overcome, it does no good when interconnects are not accessible externally.
One conventional method of (partially) solving the above-mentioned problems has been relying upon the integration of small memory arrays at various key locations on a chip to allow for the sampling of various interconnects internally. The problem with such method is that the memory arrays have to be very small in size, which means limited storage capacity, because of the cost of additional silicon areas. Even with the use of advanced data compression techniques, the storage capacity of those small memory arrays are still nowhere near the storage capacity that is considered to be useful for debugging complex sequences or collecting traces suitable for performance analysis.
Consequently, it would be desirable to provide a method and apparatus for collecting lengthy core instruction traces or interconnect traces without the use of externally attached logic analyzers or additional on-chip small memory arrays.